1. Field of the Invention
This invention relates to a field effect type thin film transistor film more particularly this invention relates to a polycrystalline silicon transistor a thin film, of which is constituted of a polycrystalline silicon thin film which is high in actuation characteristics, reliability and stability, said thin film transistor has a small interface level, small the level difference at in its time of wiring in its, and also a small capacitance between gate and source or between gate and drain.
2. Description of the Prior Art
Recently, it has been proposed to use a silicon thin film formed on a certain substrate as the base material for a scanning circuit portion of an image reading device for use in image reading such as a one-dimensional photosensor made in a continuous length or a two-dimensional photosensor of an enlarged area, and as a driving circuit in an image display device utilizing a liquid crystal (abbreviated as LC), electrochromic material (abbreviated as EC) or electroluminescence material (abbreviated as EL). A polycrystalline rather than an amorphous silicon thin film is desired for realization of a large scale image reading device or image display device improved in higher speed and higher function. The effective carrier mobility .mu.eff of a silicon thin film, for example, a field effect transistor, as base material for formation of a scanning circuit portion of a high speed, high function reading device or driving circuit portion of an image display device should be large, but that of the amorphous silicon thin film obtained by the ordinary discharge decomposition method is at most 0.1 cm.sup.2 /V. sec, which is far inferior as compared with the MOS type transistor prepared with a single crystalline silicon. Thus amorphous silicon does not satisfy the desired requirements. The small of mobility .mu.eff, partly because the Hall mobility is small as an inherent characteristic of an amophous silicon thin film, means that the ease of preparation and the low productin cost of the amorphous silicon thin film cannot be taken advantage of. Also, amorphous silicon is inferior to single crystalline silicon in that it is essentially susceptible to changes with lapse of time.
In contrast, a polycrystalline thin film is greater in Hall mobility than an amorphous silicon thin film as apparently seen from the data actually measured, and also is far greater in the mobility .mu.eff when made into a thin film transistor. Also it has theoretically a potential ability to give a thin film transistor having a mobility .mu.eff value by far greater than that presently obtained. It is also expected to be stable with respect to change with lapse of time.
As methods for forming a polycrystalline silicon thin film on a given substrate over a large area, there have been known the CVD (Chemical Vapour Deposition) method, the LPCVD (Low Pressure Chemical Vapour Deposition) method, the MBE (Molecular Beam Epitaxy) method, the IP (Ion Plating) method, the GD (Glow Discharge) method and others. It is known that polycrystalline silicon thin films are formed on substrates with large areas according to any one of these methods, although the substrate temperatures may differ depending on the methods employed.
However, at present, a semiconductor element or a semiconductor device comprising a semiconductor layer of a polycrystalline silicon thin film formed by the methods of the prior art cannot exhibit sufficiently desired characteristics and reliability.
Thin film transistors are also known, which have a coplanar structure and a staggered structure. In such thin film transistors, the upper gate is positioned at the upper part of the semiconductor layer having good crystallinity.
However, in the staggered structure, during deposition of the semiconductor layer, there is an auto-doping effect from the lower source electrode and the lower drain electrode portions into the semiconductor layer. Thus the resistance of the semiconductor layer can not be sufficiently controlled. On the other hand, in the coplanar structure, during formation of the respective electrode portions of the upper source and drain, the interface between the semiconductor layer and the insulating layer is exposed to an etchant resulting in an increase of the interface level density, which will disadvantageously lead to lowering of effective mobility. Also, in the preparation of a thin film transistor of the prior art, the doped layer is fabricated by layer lamination, whereby the junction portions of source and drain exist at the same level as that of the semiconductor layer-insulating layer interface, thus creating a marked difference in the level in wiring the upper electrode to cause discontinuities of the electrode layer.
Further, the formation of an insulating layer at the portion different in level and the formation of a gate electrode thereon will make the overlapping portion greater, thus retarding disadvantageously the actuation speed of the transistor. Also, there is the drawback that leaks may occur between the gate and source or between the gate and drain at the portions different in level.